In the continuing development of more advanced digital integrated circuit chips ("ICs"), it has been the object to make them smaller and faster. With this reduction in size and increase in the speed at which such advanced digital ICs process information, there are also physical constraints associated with the small package size and the ability to get signals on and off the chips. These constraints, which are reflected in the electronic characteristics of the package, cause problems that surface when such advanced chips are in use.
One such problem that has arisen in advanced IC chips in that only a certain number of output pins can simultaneously switch in a short, predetermined period of time without detrimentally affecting the operation of the chip. This short, predetermined period of time depends upon the digital IC and the specific IC package. But, it is now typically in the range of 2-3 ns (nanoseconds). Therefore, IC designers must ensure that the IC that they are designing does not violate the simultaneously switching output ("SSO") limit for a given digital IC chip.
Even though the SSO limit affects digital ICs generally, it poses a clearly recognized problem in emitter-coupled logic ("ECL") and metal-oxide semiconductor ("MOS") IC chips.
ECL and MOS devices have a plurality of pins. Some are exclusively input pins or output pins, while others may serve as both input and output pins. The SSO limit affects an IC chip's output scheme, but does not affect the input pins since any switching with respect to the input pins takes place off chip at the signal source.
The cycle time for advanced ECL or MOS devices, which is the period of the primary clock that controls the IC's operation, may at the present time approach 4 ns. However, it is anticipated that future devices will have cycle times shorter than this. As stated, the short, predetermined period that is associated with the SSO limit is presently in the range of 2-3 ns. This SSO limit period, therefore, may presently constitute 1/2 the cycle time. And since cycle times are trending to be shorter in the future, the SSO period may constitute more than 1/2 of an IC's cycle time in the future.
If the SSO limit is exceeded, it is not known what the effect on a particular chip's operation will be. Two of the known deviations from design specifications operation of chips caused by violating the SSO limit have been internal state changes and the instability of the outputs. Also, IC chips that have had their SSO limit violated will usually require an extended settling time before they can be used again. In sum, exceeding the SSO limit effectively renders digital IC chips useless at least for a while. These potential problems created by violating the SSO limit have caused chip manufacturers not to guarantee chip operation according to design specifications if the SSO limitation is violated.
There are some suggested methods for preventing advanced digital IC chips from violating the SSO limit; however, these methods either are very costly or require the chip processing speed to be significantly reduced.
One costly solution is to reconfigure the IC packaging. This can be done in several ways. For example, all of the output pins can be differential output pins, or the SSO limit can be raised, or a larger number of grounds can be incorporated in the package design. Another costly method is to reconfigure the chip so that the output signals are served in a lock-step fashion.
A suggested solution that affects the speed of the digital IC chip is to stagger the outputs over a longer time window. Another is to design the digital IC chip with long cycle times so that the chance of violating the SSO limit is minimal.
All of these possible solutions, however, go directly against the desire to make digital IC chips cheaper, smaller, and faster. This also has a detrimental effect on the overall system of which the digital IC chips are part. Thus, there is a need to overcome these problems associated with a digital IC chip's SSO limit without requiring a change to the chip' package design or significantly affecting the chip' processing speed.